What is Flash memory?
Flash memory is a non-volatile storage memory. It is designed to erase and rewrite or re-program at the byte level easily. It is a special type of floating gate memory. Each memory chip holds plenty of flash memory cell units. It is based on electrically erasable programmable read-only memory called EEPROM. Flash memory is a unique type of EEPROM (Electronically Erasable Programmable Read-Only Memory) designed for high speed and with high density. It typically consists of large erase blocks (Greater than 512 bytes) and with not less than 10 000 writing cycles. It stores a large amount of data in a small area using stacked memory cells. The density of the memory cells is increased significantly to cater to the demand for storing more data in a small area.
The primary limitation of Flash memory is that it can do a relatively smaller number of write cycles in a specific block. In 1980 Toshiba, a Japanese company, invented it. A Flash memory gadget consists of several flash memory chips and a controller chip.
Types of Flash Memory:
There are two types of flash memory. They are:
- NOR Flash memory (NOR Flash, the correlation between the bit line and the word lines resembles a NOR gate)
- NAND Flash memory (NAND flash, the correlation between the bit line and the word lines resembles a NAND gate)
They are named after the logic gates they use in writing and rewriting. They use the cell design consisting of metal–oxide–semiconductor field-effect transistor in a floating gate. Both of them differ in many aspects, including circuit level. Microcontrollers also use it for writing and executing firmware. The NAND memory is typically significantly smaller in size. As a result, they may be erased, rewritten, and read in blocks. At the same time, NOR memory allows a single machine word to be erased, rewritten, or read in a location independently.
NAND type memory is used in memory cards, old model solid-state drives, mobile phones, and USB flash drives. NOR memory is also used to store more critical configuration data in various digital products, battery-operated Static RAM. Their purpose is to work as general storage and transfer of data.
How It Works:
It comes with inbuilt solid-state chips. In addition, each chip has an array of flash memory cells.
Flash memory uses electrical circuits to log data. The current flows through the transistor between each cell source and drain. The transistor regulates the path and functions as an on-off switch or gate.
The transistor allows current to flow across the cell at the ON position, which stores binary code “1”. At the OFF position, the transistor blocks the current flow and stores the value “0”.
Flash Memory is used in computers, handheld Pcs, personal digital assistants, digital audio players, digital cameras, mobile phones, synthesizers, video games, medical and scientific instrumentation, and robots. Its memory latency is significantly less, and it has a fast read access time. On the other hand, it is comparatively slow compared to ROM or RAM. It has high mechanical shock resistance and is therefore used in some portable devices vulnerable to mechanical shock. Flash memories have a significant advantage over other non-flash EEPROM. It has large block sizes.
Furthermore, their erase cycles are very much slow. Therefore erasing large blocks gives it a good speed advantage while writing bulk data. Comparatively, Flash EEPROM costs much less than the byte programmable EEPROM.
It is significantly employed in non-volatile solid-state storage. Using die stacking of three-dimensional integrated circuits in vertical interconnection, flash memory packages can be raised to the capacity of up to 1 TB. It needs at least 16 vertically connected stacked dies with one integrated flash controller inside the package to get the storage capacity of one tebibyte (240 Bytes)
The idea of flash memory was started to develop from the origin of FGMOS or floating gate transistors, which are used in floating gate memory cells. Earlier, the EPROM and EEPROM were included in the floating gate memory. However, it requires a lot of manpower to build a memory cell for each bit of data, which is expensive and more time-consuming.
In 1980 Fujio Masuoka, working at Toshiba, designed a type of floating gate memory that erases the entire section of memory very easily in lesser time. He applied voltage to a wire-connected group of cells in the memory. It leads to the invention of flash memory. The name Flash was recommended by Shoji Ariizumi. In 1984 they invented NOR Flash and then NAND flash in 1987.
Unfortunately, when Masuoka presented it at the annual International Electronics Developers Meeting in 1984, the world of American scientists saw it as a threat. So Toshiba launched the NAND flash memory in 1987. One year later, Intel launched its NOR flash chip memory.
NOR Type Memory:
NOR-type memory has a long write and erase time. However, it provides full address and data buses allowing random access to memory location. Therefore NOR-type memory is suitable for the replacement of ROM Chips. Programs stored in ROM very rarely need to be updated. So it is a better replacement for ROM, which stores such programs in BIOS, the firmware of set-top boxes. It can be used to a maximum of 100,000 erase cycles. Initially, the Compact Flash was based on NOR, and it later moved on to NAND to control the price.
NAND Type Memory:
NAND flash has lesser erase and write time. In addition, it requires less chip area per cell. Therefore it has a higher storage density and lower cost than the NOR flash. However, the disadvantage is that the I/O interface of NAND flash does not possess a random-access external address bus.
Therefore Data must be read on a block-wise basis with block size varying from hundreds to thousands of bits. This makes the NAND flash unsuitable for the replacement of ROM since most of the processors and microcontrollers require byte-level random access. Therefore NAND flash is best suitable for secondary storage devices such as hard disks and optical media. It is best suited for mass storage devices such as SSD and memory cards. They will have multiple inbuilt NAND flash memory chips.
Due to the latest technological advancement, the memory density of NAND flash is highly improved and commercialized.
Charge Trap Flash (CTF):
CTF is a semiconductor memory technology used to create non-volatile NOR and NAND flash memory. It is another type of floating gate MOSFET memory technology. The conventional floating gate technology uses polycrystalline silicon film to store electrons, but the CTF doped the conventional technology using polycrystalline silicon as a floating gate structure and replaced it with silicon nitride film.
CTF replaced Poly-silicon floating gate technology. CTF is sandwiched between blocking gate oxide above and a tunneling oxide below it, with an electrically insulating silicon nitride layer. The silicon nitride layer traps electrons. This CTF technology provides better data retention with zero electron leakage. Conversely, the electrons become more excited with increasing temperatures; therefore, electrons leakage may happen at a higher temp.
However, Charge Trap Flash still uses a tunneling oxide and blocking layer, which are the two negatives of that technology. The Blocking layer may get damaged due to anode Hot Hole Injection, and the tunnel oxide may get damaged due to the extremely high electric fields. Therefore the oxides must be unsalted against the electrons to prevent the electron leaking, which may lead to data loss. With increasing wear of oxides, the data retention may go down. Furthermore, the degradation of oxides may directly affect the endurance of the memory since the oxides lose their insulating characteristics as they degrade. In 1991, the NEC scientists implemented Flash Memory with the charge trap method.
Later in 1998, NROM flash memory technology was introduced. They replaced the traditional floating gates with a charge trapping layer in conventional flash memory design. In 2002 Vertical NAND technology-based flash memory cells started using 3D charge trap flash technology vertically within the chip. Toshiba introduced 3D V- NAND technology, and the first device implemented 3D V- NAND with 24 layers came to the market in 2013.
3D IC (3D Integrated Circuit) Technology:
This technology loads IC chips vertically into a single 3D IC chip package. Next, Toshiba introduced 3D IC into NAND flash memory. Later in 2010, 3D ICs came into widespread commercial utilization and use of NAND memory in mobile gadgets. Then in 3D V-NAND with eight stacks, 64 layers came to the market.
Flash Memory Working Principle:
Flash memory has an array of memory cells made from floating-gate transistors in which Data is stored. In single-level cell memory devices, each cell stores only one bit of information, whereas in Multi-level cells, including TLC, data can be stored more than one bit per cell. Besides, there are two types of floating gates, namely conductive and non-conductive. In Floating Gate, polysilicon is employed in both conductive and non-conductive.
Floating Gate MOSFET:
In flash memory, each cell resembles MOSFET (metal-oxide-semiconductor field-effect transistor). However, it varies with the MOSFET transistor gate. MOSFET has only one gate, whereas the other has two gates. Each cell works as an electrical switch in which current flows between source and drain. Further, it is controlled by a floating gate and a control gate. The control gate functions similar to the gate in the MOS transistor. But below the control gate, a floating gate is placed. The floating gate is insulated entirely using an oxide layer. The floating gate is placed between the control gate and the MOSFET channel.
Since the insulating oxide layer electrically isolates the floating gate, the electrons held within them are trapped.
How Data is Stored:
When the floating gate is charged with electrons, the increase in charge screens the electric field from the control gate, increasing the cell’s threshold voltage (VT1).
Therefore, a higher voltage (VT2) must now be applied to the control gate to make the channel conductive. In order to read the binary value from the transistor, an intermediate voltage between the threshold voltages must be applied to the control gate.
If any of the channels conduct at this intermediate voltage, the floating gate must be uncharged (if the floating gate is charged, the intermediate voltage will be less than VT2 conduction will not happen. Further, if the conduction happens, then logical “1” is stored in the gate; if the channel does not conduct at the intermediate voltage, it implies the floating gate is charged, and therefore a logical “0” is stored in the gate. The presence of “0” or “1” is identified by determining where there is current flowing through the memory transistor when the intermediate voltage is asserted on the control gate.
In Multi Level Cell Device:
Data can be stored more than a bit per cell in a multi-level cell device. Therefore the amount of current flow is sensed to identify the level of charge on the floating gate. There is an electrically insulated tunnel oxide layer between the floating gate and the silicon; therefore, the gate floats above the silicon. Moreover, the oxide layer keeps the electrons confined to the floating gate. In the long run, degradation or wear may occur due to the extremely high electric field experienced by the oxide. This high voltage density can break atomic bonds overtime on the relatively thin oxide coating. Thereby it gradually loses its insulating properties and allows the trapped electrons to move freely, resulting in electron leak from the floating gate, which may lead to data loss.
What is Fowler Nordheim Tunneling?
Fowler Nordheim Tunneling is the process of moving free electrons from the control gate and into the floating gate. By doing so, we are changing the characteristics of the cell by increasing the MOSFET’s threshold voltage. In turn, it changes the source current that flows thro’ the transistor for a given gate voltage; it is used to encode the binary value to the cell. Fowler Nordheim Tunneling is a reversible process; therefore, electrons can be added to or removed from the floating gate. Adding or removing the electrons from the floating gate is known as writing and erasing.
Internal Charge Pumps:
To erase and program, it needs high voltages, but the latest flash chips require a single supply voltage, and they produce high voltages of their own using the on-chip charge pumps. The charge pump is similar to DC to DC converter that uses capacitors to raise the voltage. With simple circuits, the charge pumps can do high erasing voltages. However, the charge pumps may fail in high radiation environments.
Each cell in the NOR Flash’s one end is directly grounded, and the other end is connected directly to the bit line. This arrangement behaves as the NOR gate. While one of the word lines connected to the control gate is brought high, the relative storage transistor will pull the output bit line low. For embedded applications that require distinct non-volatile memory, the NOR Flash suits best. Their low read latencies allow both direct code execution and data storage in single memory products.
The default state of the single level NOR-Flash cell is logically equal to the binary value 1. Since the current flow through the channel by applying the appropriate voltage to the control gate, the bit line voltage is pulled down. NOR flash memory cell can be programmed or set to a binary value of 0 by following the steps:
Apply elevated voltage to the control gate
Now the channel is turned on, and electrons can flow through the source to the drain
The source-drain current is sufficiently high to make some high-energy electrons jump through the insulating layer onto the floating gate.
A high reverse polarity voltage is applied between the control gate and source terminal to erase the NOR-Flash cell and pulls the electrons off the floating gate through quantum tunneling. The latest model NOR chips are divided into multiple erase segments called blocks or sectors. The erasing operation can be done block-wise. Moreover, all the cells in the erase segment will be erased altogether. The Programming of NOR cells is done one word or byte at a time.
NAND flash uses floating-gate transistors connected in the same way as NAND gate. Several transistors are connected in series. Further, the bit line is pulled low if all the word line is pulled high above the VT. In addition, this group is connected through some additional transistors to a NOR style bit line array in the same method as a single transistor linked in NOR flash.
Replacing single transistors with serially linked group add more level of addressing. Due to serially linked transistors, NAND flash can address it by pages, word, and bit, whereas the NOR flash memory can address by word. This bit-level addressing best suits bit-serial applications such as hard disk emulation, which can access only one bit at a time.
To read data, the desired group is first selected in a similar way the NOR array selects. Then most of the word links are pulled up above the VT of the programmed bit when one of them is pulled up to just over the VT of an erased bit. Even though there are additional transistors, a reduction in the number of ground wires and bit lines allows a tightly packed layout with higher storage capacity per chip. Besides, the NAND flash is generally permitted to contain certain number of faults. The latest models are more compact since the manufacturers are maximizing usable storage by minimizing the size of the transistors.
NAND Writing and Erasing:
Tunnel injection and Tunnel release are used for writing and erasing in NAND flash. It is used in removable USB devices called USB flash drives. Besides, most memory cards and solid-state drives have NAND flash type.
The NAND flash structure starts from cell level to strings, then pages, blocks, planes, and a die. A string is a series of connected cells in which the source of one cell is connected to the drain of the neighboring cell. Generally, the NAND string consists of 32 to 128 NAND cells. Besides, strings are organized into multiple pages. Further, the pages are organized into blocks in which each string is connected to an individual line called a bit line.
The cells, which are in the same position in a string, are connected through the control gate by a word line or WL. In addition, the plane contains a definite number of blocks that are connected through the same bit line or BL. Moreover, the Die consists of one or more planes connected by the circuit wiring that needs to do the read, write and erase functions.
In NAND flash, the data can be read and programmed in pages typically between the size of 4KiB and 16KiB. However, it can be erased only on the entire block level, consisting of multiple pages.
How Flash Memory Read and Write:
When a page is erased, all the cells in the blocks are logically set to “1”. Any cell that has been set to “0” by programming can be reset to “1” only by erasing the entire block. New data can be fed into a page; if the page already contains any data, then the current content of the page plus the new data will be copied to a new erased page. Further, if a page is available to copy then, the data will be written to it immediately.
If no erased page is there, then an entire block should be erased before copying the data to a page in that block. The old page will be marked invalid, and it is available for erasing and reusing. To prevent early failure in the page, the controller meant for wear leveling ensure all blocks are used equally. The data will be moved to one of the least used pages. If the repeated failure occurs when erasing the block, that block is marked as bad and will not be used further. Flash memories are built with excess spare blocks; they can handle the bad blocks easily.
In V-NAND, memory cells are stacked vertically, and it uses a charge trap flash architecture. The vertical layers allow larger bit densities without requiring smaller individual cells.
V- NAND uses a charge trap flash that stores the charge on an embedded silicon nitride film, and it is purposely made thicker to hold a large number of electrons. It warps the planar charge trap cells in a cylindrical form. In 3D NAND floating gate, the memory cells are entirely isolated from one another, but in Charge Trap, the 3D NAND, vertical groups of memory cells share the same silicon nitride materials.
Every memory cell is made up of one planar polysilicon layer containing a hole filled by multiple concentric vertical cylinders. These holes act as gate electrodes. The outer-most silicon dioxide cylinder acts as the gate dielectric, enclosing a silicon nitride that stores the charge.
The memory cells in different vertical layers do not interfere with each other. The vertical collection is electrically similar to the configured series linked group. As a result, the V-NAND Flash is double time faster than the conventional NAND.
Flash Memory Limitations:
The flash memory can read or programmed a word or a byte at a time in a random access fashion, but it can be erased only on, by blocks. Once erased, all bits in the block will be 1. Any cell within the block can be programmed in a freshly erased block. Once any cell bit has been set to 0 to change it back to 1, we need to erase the entire block.
The NOR flash offers random access, read, and programming operations, but it will not offer a random-access rewrite or erase function. But a location can, however, be rewritten as the new value “0” bits are the superset of the overwritten values.
The data structure cannot be updated completely, but it can be removed, marking them invalid.
Each cell may hold more than one bit in multi-level cells, so this technique may need to be modified.
Memory cards and USB flash drives are only block-level interfaces or flash translation layers. It helps to control write to a different cell each time to control the wear level of the device. In addition, it prevents incremental writing within a block.
Memory wear- It has a finite number of program erase cycles
A flash memory without wear leveling will not last for long. If there is no wear leveling, every write to a previously written block will be first read, erased, modified, and rewritten in the same location, and it will consume more time and wear out quickly. Besides, the other locations will not be used at all in the entire life cycle.
The X-ray can erase the program bits.
The memories that have to go through a large number of programming cycles cannot be a flash memory unit.
NOR Memories Management:
The reading method may cause nearby cells in the same memory block to change over time in NAND memory. It is called read disturb. If reading continuously from one particular cell, that will not fail but the surrounding cells on a subsequent read. The flash controller will count the total number of reads to a block since the last erase to overcome the read disturb issue. When the count exceeds the target limit, the block is copied over a new block, erased, and released the block pool. The new after-erase is fine as the original block. If the flash controller is not function and intervenes in time, the Read Disturb Error will occur with some data loss if the errors are many.
The NOR memory has an external address bus for Reading and Programming. The Reading and writing are done on page-wise, and erasing and unlocking are done on block-wise. But in NOR, Reading and writing is at random access, and unlocking and erasing are done block-wise.
The reading process in NOR- Flash is similar to reading from RAM by providing the address and data bus mapped correctly. With this feature, the processors can use the NOR memory as execute in place memory. The programs stored in NOR flash can be executed directly from the NOR without the need of copying from the RAM first. The NOR flash can be programmed in a random-access manner similar in Reading. The block sizes are 64, 128, or 256 KiB. The latest NOR chips come with Bad Block Management. It is controlled by the device driver controlling the memory chips that handle the blocks that wear out. A typical NOR Flash does not need an error correction code, and they have very slow writing speed when compared to NAND chips.
NAND Flash Memories:
The ECC will correct a one-bit error in every 2048 bits using 22 bits of ECC. Even if ECC cannot correct the error during the read, it can detect and point out the error. For example, during Erasing, the device can detect the blocks that fail to erase and mark them as bad. Then the data can be written to the different blocks, and the bad block map will be updated, including the present bad block. Generally, NAND flashes are shipped from the manufacturer with some bad blocks.
Moreover, they are marked as bad blocks according to the bad block marking strategy. NAND is best suited for the systems which require high volume data storage. It offers higher density with greater capacity at a lesser cost. It is swift to erase, sequential write, and read.
ONFI is a consortium of technology companies developed to standardize the low-level interface for NAND flash chips. Its objective is to make it easier to switch between NAND chips from various producers to develop NAND products at a lower cost. In addition, it ensures interoperability between the NAND devices from various vendors.
It specifies the following:
Standard pinout for NAND devices
Standard set of commands for reading, writing, and erasing
A fault-free mechanism for self-identification similar to SPD (serial presence detection)
Difference between NOR and NAND:
- The connection to the individual memory cells varies.
- The interface for reading and writing the respective memories are different.
- The NAND allows only page access, whereas the NOR allows random access.
- Nor Cells are larger than the NAND cells since they need separate metal contact for each cell.
- NOR flash cells are connected in parallel, and NAND flash cells are connected in series.
- The series connection occupies less space than the parallel one. Therefore NAND flash is cheaper than the NOR.
- With the series connection and removal of word-line contacts, a large grid of NAND flash cells occupy lesser space when neither compared with NOR cells.
- The cost of the NAND cell can be further reduced by removing the external address and data bus circuits. Instead, the external device can communicate with the cells through sequentially accessed commands and data registers.
- NAND flash can replace the mechanical hard disk, whereas NOR flash can replace the ROMs.
- Write endurance of NOR flash is typically greater than NAND flash.
- The 3D NAND performance may degrade if more layers are added.
Flash File System:
It is a file system designed to store the files on flash memory-based storage devices and gadgets. Though it is similar to the file system in general, it is optimized for the nature and characteristics of the flash memory. It can avoid write amplification. Write amplification is an undesired phenomenon associated with it.
In flash memory, it must be erased before it should be rewritten. The erase operation is more delicate and complicated than the write operation. While writing or rewriting, it needs to do moving user data and Metadata more than once. The rewriting process requires an already used portion of Flash to be read and updated, and written to a new location together with the initially erased location if it was used at some point of time.
Due to the nature of its working, a much larger portion of Flash must be erased and rewritten than the actually required amount of data. As a result, it multiplies and increases the number of write requests tremendously. Therefore it shortens the reliable operation time. Besides, it increases the bandwidth of the flash memory, which directly affects the random write performance. On the other hand, reads do not require an erase of the memory. Therefore, they will not be affected by write amplification, but the read disturbs error may happen in that block that is going to read and rewrite.
We know the Data is written on memory at the page level, which is made up of multiple cells. But the memory can only be erased in larger units called blocks that are made up of multiple pages. If the data in some of the pages of a block are no longer needed, then the pages with good data in that block are read and rewritten into another previously erased vacant block. The free pages with the stale data are available now for new data writing.
This process is named as garbage collection. It is best used with a controller to do Wear Leveling and Error Correction that is specially designed for flash file systems to overcome these issues. The basic concept is that when the flash storage is updated, the file system of the memory will write a new copy of the changed data to a new block and re-map the file pointer, then erase the old block later when it has time.
The memory cards, SSDs, and USB flash drives have inbuilt controllers to perform the error corrections and wear leveling.
The file system is optimized to handle erasing the blocks. As a result, flash memories devices impose no seek latency. In addition, flash file systems are designed to spread out writes evenly to avoid wear leveling.
Flash Memory Capacity:
More chips are often dying stacked to achieve higher capacities in most of the devices. The flash memory is made of interrogated circuits and techniques; increasing the capacity of flash chips is always following Moore’s law. However, in the latest devices, after introducing 3 D NAND scaling, Moore’s law is no longer applicable since the tiny transistors are no longer used. Typically the size of the memory capacity is expressed in multiple powers of 2s, Such as 4 GB, 512MB, etc. The capacity available for file usage is slightly lesser than the size expressed. It is due to the space occupied by the file system Metadata.
The memory chips are sized in strict binary multiples. It is considerably larger than the labeled capacity. But some space is occupied and allotted for distribution of Write Wear Leveling, Sparing, Error Correction codes, metadata, and internal firmware.
Flash memory is much faster at Reading than at writing. Further, its performance depends on the storage controller. The work of the storage controller is critical when the storage is partially full. The absence of any appropriate controller can result in degraded speeds.
Applications of Flash Memory:
It is a tiny low powered flash memory that can only provide serial access to the data instead of addressing the individual bytes. It reads or writes a large closest group of bytes in the address space serially. The serial peripheral interface bus protocol is used to access the data. When serial Flash is included into an embedded system, it requires only very few wires on the printed circuit board than the parallel flash memory. It transmits and receives Data only one bit at a time. It allows a reduction in board space, power consumption, and total system cost.
Elimination of bond pads permits more compact and elegant ICs on smaller die. It, in turn, helps increase the number of dies on a wafer. And thereby minimize the cost per Die. Furthermore, it eliminates the number of external pins used and thereby reduces the packaging and assembly expense. As a result, a serial flash drive device can occupy lesser space than a parallel-connected flash device.
Less number of pins occupies a lesser PCB area and minimizes the overall size. Further lesser number of pins simplifies the PCB routing.
There are two types of serial peripheral interface (SPI) flash types. The first type is of all small pages that have only one or more internal SRAM page buffers allowing a complete page to read the buffer and partially modified and then write back. The second one has larger sectors. These types do not have an internal SRAM buffer. Therefore complete page must be read out and modified before being written back, making it slow to manage. The second type is cheaper. Unfortunately, these two types do not have the same pinout; they are incompatible and not exchangeable.
Modern Central Processing Units are of higher speed, but the parallel flash devices are often much slower than the memory bus of the motherboard they are connected to. The modern DDR2 SDRAM offers access times much below than 20 nanoseconds. So it is more advantageous to allow the shadow code stored in Flash into RAM. For that, the shadow code is copied from Flash into RAM before execution so that it may access it at full speed. The device’s firmware is stored in the serial flash device and then copied to the RAM when the device is powered up. Using a serial flash device is better than using the onboard chip flash removes the need for significant process compromise.
Flash Memory as Hard Drive Replacement:
One of the most recent developments in flash memory applications is that it is treated as a replacement for hard disks. When compared, it does not have the mechanical limitations and latencies of the hard drive. Therefore the Solid-state drive is better when considering the speed, noise, power consumption, and reliability. Now they are used as a substitute for the hard drives in high-performance desktops.
The cost per gigabyte of flash memory is significantly higher when compared to the hard disks. The deleted files on SSDs can remain for a long time before being overwritten by the fresh data. The software or erasing techniques have no effect on SSDs. Using the TRIM command, the solid-state drives can mark the logical block addresses of the deleted files as unused to enable garbage collection. Even data recovery software cannot restore the files deleted in such a way.
The Archival or Long Term Storage:
The floating gate transistors in the storage device hold the charges that represent the data. However, this charge gradually leaks over time. That will lead to more logical errors that are known as bit rot or bit fading. It is not clear how long the Data on the flash memory will stay secured under archival conditions. The retention span varies with the model and type of storage. When connected to the power and staying idle, the charge of the transistors that hold the Data is routinely refreshed by the storage firmware. Therefore the ability to retain data will be affected by the following factors such as data redundancy and error correction algorithms.
Due to its simple design and structure and high demand, NAND flash memory is the most belligerently scaled technology. Due to high demand and competition on the higher capacity flash drives, they are shrinking the floating gate MOSFET design rule. As a result, the MOSFET feature size of the cells reaches a 15 to 16nm limit, and the density increases to 3 bits per cell combined with the vertical stacking of NAND memory planes.